The present invention relates to methods of fabricating MOS-gated semiconductor devices, and more particularly to such a method in which the number of diffusion steps is reduced from two to one.
Semiconductor devices are fabricated in multi-step processes in which each step is costly and time consuming. The need for each step is carefully analyzed and steps are eliminated or consolidated whenever possible. The cost and time saved by elimination of even a single step makes a process in which such an improvement is found a valuable asset.
By way of example, MOS-gated semiconductor devices are typically fabricated in steps which include: forming the wafer with junctions as will be needed beneath the gate structure, growing a gate oxide, depositing polycrystalline silicon (polysilicon) on the gate oxide, patterning and etching the polysilicon to form a gate electrode as well as a mask for channel and source dopants, implanting a P type dopant through openings in the polysilicon mask to form the channel region, forming a further mask for the P+ dopant which will form the body region, implanting the P+ dopant through the further mask, diffusing these dopants in a first diffusion operation, implanting the N+ source region dopant through the openings in the polysilicon mask, and then diffusing this dopant in a second diffusion operation. FIGS. 5(a)-5(c) respectively illustrate a MOSFET, IGBT and an MCT which may be made by such typical fabrication steps.
The present invention is directed, at least in part, to a method of consolidating the two diffusion operations in the above, although the method will find application in a variety of semiconductor device fabrication operations and is not limited to the process above.
Accordingly, it is an object of the present invention to provide a novel method of fabricating a semiconductor device in which the number of diffusion steps is reduced from two to one, thereby obviating the problems of the prior art.
It is another object of the present invention to provide a novel method of fabricating a semiconductor device in which a first conductivity type dopant is implanted through a mask opening to form a first layer, and a second conductivity type dopant is implanted through the opening to form a second layer deeper than the first layer, where the second conductivity type dopant has a faster diffusion rate than the first conductivity type dopant and a propensity to migrate into high concentrations of the first conductivity type dopant, and in which the first and second conductivity type dopants are diffused in a single diffusion operation.
It is yet another object of the present invention to provide a novel method of fabricating an MOS-gated semiconductor device in which arsenic is implanted to form a first layer, boron is implanted to form a second layer deeper than the first layer, and in which a single diffusion of the implanted arsenic and boron forms a P+ body region with an N+ source region therein and a P type channel region.
It is still another object of the present invention to provide a novel method of fabricating an MOS-gated semiconductor device in which a polysilicon gate forms a mask through which structures in the substrate are to be formed, arsenic is implanted at a first dose and a first energy level through the mask openings, boron is implanted at a second dose and a second energy level through the mask openings, and in which a single diffusion forms a structure with a P+ body region with a dopant concentration of from 1.times.10.sup.18 /cm.sup.3 to 1.times.10.sup.19 /cm.sup.3 beneath an N+ source region therein and a P type channel region with a dopant concentration of from 1.times.10.sup.17 /cm.sup.3 to 5.times.10.sup.17 /cm.sup.3.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.